How to boot board from EPCS with NIOSII code running from SDRAM?

Hi hareesh,

Actually the design is provided by Intel as I said in my first thread, this is the original source: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Can-t-get-DE0-nano-board-to-boot-from-EPCS-with-NIOSII-code/td-p/698479

And I opened the design with Quartus lite v18.1, I can see the SDRAM controller without any problem.