New ContributorHow to access the EMIF HPS subsystem DDR (1TB) via Agilex 5 HPS (265GB)
Hello everyone,
I am trying to access the EMIF for HPS DDR with the HPS in a first test design to get to know the Altera Design Flow. However, I get the following error (see attachment):
- emif_hps_ph2_0.s0_axi4 (0x0..0xffffffffffff) is outside the master's address range (0x0..0x3fffffffffff)
- axi_bridge_0.s0 (0x0..0x3fffffffffff) overlaps emif_hps_ph2_0.s0_axi4 (0x0..0xffffffffffff)
- Error: Width of agent ID signals (10) must be at least 11. Increase agent ID width or reduce ID widths for any connected AXI managers
I tried to limit the address range of the EMIF HPS to the address range of the HPS2FPGA bridge using an AXI bridge, but it is probably not possible to set the end address. I also could not find a kind of address remapper in the IPs, Is it not possible to leave the higher addres lines open?
Is it possible to access the DDR in this way or how should such a design look like?
Hi
The HPS EMIF is connected to the IO96 of the HPS connection. You do not need to add in an axi bridge for this.
You could enable this under the SDRAM tab of the Agilex5 HPS IP.
You could try taking a look at the GHRD for the Agilex5 from the link below:
Regards
Jingyang, Teh
