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Wizard123's avatar
Wizard123
Icon for New Contributor rankNew Contributor
1 year ago
Solved

How to access the EMIF HPS subsystem DDR (1TB) via Agilex 5 HPS (265GB)

Hello everyone, I am trying to access the EMIF for HPS DDR with the HPS in a first test design to get to know the Altera Design Flow. However, I get the following error (see attachment): - emif_h...
Fpga Devkit
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi

The HPS EMIF is connected to the IO96 of the HPS connection. You do not need to add in an axi bridge for this.

You could enable this under the SDRAM tab of the Agilex5 HPS IP.

https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/emif-ip-for-hard-processor-subsystem-hps.html

You could try taking a look at the GHRD for the Agilex5 from the link below:

https://altera-fpga.github.io/rel-24.2/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/#ghrd-overview

Regards

Jingyang, Teh