Forum Discussion
AnilErinch_A_Intel
Frequent Contributor
5 years agoHi ,
You can enable the FPGA2HPS bridge in the Qsys and then use the peripheral pin multiplexing technique to access FPGA data through GPIO in HPS.
Please refer to Connecting Unassigned Pins to GPIO
section in the below document
https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
also the below link from terasic can also help in understanding about the bridges., between HPS and FPGA.
http://www.terasic.com.tw/wiki/DE10_Advance_revC_demo:_AXI_bridges_in_Intel_SoC_FPGA
The following video can also help to get a start
https://www.youtube.com/watch?v=RTmDgNXIwKQ
Please let us know the progress.
Thanks and Regards
Anil