How much space does Arria 10 partial reconfiguration use?

Hi, we are exploring Arria 10 Partial Reconfiguration over PCIe and are concerned how much device space will be "wasted" in single region Partial Reconfiguration comparing to the same design without using any Partial Reconfiguration. Can Intel provide such info as, for example, percentage of logic fabrics "wasted" that can be otherwise used for logic if not for partial reconfiguration? I understand that it is design dependent, but would appreciate it if Intel has some spread sheet to show some statistical results, or if not, some range of percentage. Thanks.