How much space does Arria 10 partial reconfiguration use?

You can set the Logic Lock placement and routing regions to whatever size you want, so you can size them to *just* fit the largest persona for your PR region logic if you want though that doesn't give you room to grow.

PR does add wire LUTs (logic stubs essentially; just a few gates) at all the I/O ports of the PR region, so the more I/O to the region, the more wire LUTs required.

Check out the online training (and its related trainings) for more details:

https://www.intel.com/content/www/us/en/programmable/support/training/course/opr201.html

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