Forum Discussion

New Contributor

4 years ago

How does my SoC access FPGA IP Cores ??

Hi, I'm using Altera Cyclone V SoC, and I'm trying to access FPGA sides (the IP cores, for example, the FIFOed Avalon Uart IP Core). In NIOS II, the IP cores use the Altera HAL drivers included in ...

AnilErinch_A_Intel

Frequent Contributor

4 years ago

Hi Duc Thang,

The communication to the FPGA side peripherals from the HPS is achieved through the use of bridges.

You can see the below link for a UART IP access methods.

https://forum.rocketboards.org/t/from-hps-how-to-sending-and-receive-from-fpga-uart-altera-uart-qsys-ip/995/8

Also the video below talks more about the bridges.

https://www.youtube.com/watch?v=RTmDgNXIwKQ

Thanks and Regards

Anil

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How does my SoC access FPGA IP Cores ??

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