How can we generate a design for FPGA2 on Stratix V Advanced Systems Development Kit without any timing violations within the DDR3 SDRAM Controller IP Component?

Thank you for your reply! Your explanation sounds plausible to me, although I was hoping for an error case with a simpler solution.

Since there is a clear difference in performance between both Stratix V FPGAs, we assume that these problems have a crucial impact on our use case.