Forum Discussion

SAnan1's avatar
SAnan1
Icon for New Contributor rankNew Contributor
7 years ago

How are number of lanes in PCIe related to the actual data width I use in my application logic?

I am very confused about these things: [a] Transfer rate [b] Throughput [c] line rate [d] width of data transfer [e] PCIE Express version [f] number of lanes [g] PCIE Express generations Plea...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

​Hi,

If you are using difference lanes number, e.g from x8 to x4, the bandwidth will be reduced, but the data width can be the same as the PCIe core clk can be reduced. In the PCIe HIP GUI, you should be able to see the option in the Hard IP mode.

Regards -SK

SAnan1's avatar
SAnan1
Icon for New Contributor rankNew Contributor
7 years ago

I have updated the question. Can you please break it down further. Please....with a very simple example.