Forum Discussion
MDavi14
New Contributor
New ContributorHost Pipes OpenCL
Hi, I am working with an Stratix 10 GX development kit, and I have a problem with the example design loopback_Host Pipe. When the host communicate with the OpenCL command clSetKernelArg(kernel, 0, s...
MDavi14New Contributor
New ContributorThe source code that I used is the example in:
https://www.altera.com/support/support-resources/design-examples/design-software/opencl/host-pipe.html,
The aocl version is:
aocl 18.1.0.222 (Intel(R) FPGA SDK for OpenCL(TM), Version 18.1.0 Build 222 Pro Edition
That means, the 18.1 do not have support for the host-pipe example such as the software and hardware requirements suggest?.
KennyT_altera
Super Contributor
Super ContributorYes, I would suggest you use the example design base on the software requirement.
