Hi, iam using MAX10-10M04DAF256C8G in one my design, i understand from Power management file for the same FPGA that Power Sequencing circuit is not required. Please correct if my understanding is wrong.

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rahul_s_intel1 · Answer

Hi,Kindly refer the document ,for your reference and you can find that there is no power up and power down sequence.https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_pwr.pd

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Hi, iam using MAX10-10M04DAF256C8G in one my design, i understand from Power management file for the same FPGA that Power Sequencing circuit is not required. Please correct if my understanding is wrong.

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