Hi , I am working with DE10-nano board to access external DDR3. FPGA-to-HPS SDRAM Interface- AXI3 is not working properly(axi_awready is always low)

Dear NKRIS7,

I am sorry for the delay in response as I had to attend company's meeting yesterday. I truly apologize for the delay.

The waitrequest is a mechanism for throttling the source of traffic to the IO Slave port. If the waitrequest is asserted High (or in other word axi_awready is always low) , it means the IO slave port does not have enough resources to keep accepting the write burst. It requests some time to wait for data processing. So, may I know for how long is the waitrequest remain high ? Is it too long ?

By the way, I found a project on RocketBoards utilizing FPGA2SDRAM interfaces:

https://rocketboards.org/foswiki/Projects/CycleVSoCSDRAMPerformanceExampleDesign

Perhaps you can take a look on that. 😊

Also you may want to read through this KDB solution and check if any setting miss out :

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html

Thanks

Regards,

NAli1