Forum Discussion
Altera_Forum
Honored Contributor
17 years agoI changed the code completely because I have too much misstakes!^^
now these I have done: module test_veri( SW_OE, SW_WE, CLK_50, LEDG, CE, WP, RESET, BYTE, OE, WE, Adress, Data, LED ); input CLK_50; input SW_OE; input SW_WE; output [2:0] LEDG; output CE; output WP; output RESET; output BYTE; output OE; output WE; output [21:0] Adress; output [15:0] LED; inout [15:0] Data; reg [2:0] LEDG; reg [15:0] LED; reg [15:0] Data; assign CE = 0; assign WP = 1; assign RESET = 1; assign BYTE = 1; assign OE = SW_OE; assign WE = SW_WE; assign Adress = 1; always @(posedge CLK_50) begin if((SW_OE==0)&&(SW_WE==1)) begin LEDG = 3'b100; LED = Data; end else if ((SW_OE==1)&&(SW_WE==0)) begin LEDG = 3'b010; Data = 16'hBDE7; end else begin LEDG = 3'b001; LED = 0; end end endmodule is that what you mean with the OE and the WE? in the datasheet is wrote that for the read-operation for example the CE# has to be at Low, have it to be 1 or 0 ? its a little bit confusing. is it now right?^^ ok...and the other point...why would it not work?I mean...I have the read and write operation in it...what do I need else that it would work?