Help with DE0 Nano and EPCS Programming

Hi All,

I know this has come up before because I've looked through many posts in the forum regarding this topic. I am currently working on a nios II based design using the DE0-Nano board and the on board 32Mb sdram. I am at the point where I want to load the hardware design and software onto the EPCS so the board can operate in a standalone situation. I can easily get the hardware design loaded into the flash but I have failed at every attempt to load the software. There's a lot of outdated documentation and conflicting forum posts about this process so I was hoping someone could lend me some guidance. My system is as follows:

Quartus v15.0

Qsys system:

50Mhz system Clock

System and SDRAM Clocks for DE-Series boards

jtag_uart

nios2_gen2_0: niosII/e During Development the reset and exception vectors have been set to the SDRAM

nios_custom_instruction: floating point custom instruction

performance counter

SDRAM Controller

SYSID

ADC controller

i2c controller

pio

uart

I am using a lot of HAL libraries and am not using the small c option. I mention this because the method of programming a bootable system in the de0 nano literature (initializing on-chip memory with program code) is not an option due to the size of my code.

If I understand correctly, what I need to do is convert my .sof and.elf files and then concatenate them together and load them to the flash chip. I then need to point the reset vector to the starting address of the code in flash. When I look in qsys I have the following options:

Legacy EPCS/EPCQx1 Flash Controller

Altera Serial Flash Controller : this one gives me the option to choose my specific device EPCS64.

Which should I use what other hardware is required? I have read in various posts that you need to use a tristate conduit or a pll for a slower clock, but then other posts don't mention any of this. Again, if anyone could provide some guidance I would greatly appreciate it. Thanks.