Help required on Ethernet with FPGA

Hi Jacob Jones,

I wanted a help from you to solve this issue of mine. I use a Nios II/s cpu, on-chip memory, SSRAM, JTAG along with a custom MAC designed by H/W team. The problem that i face is this. I tried sending and receiving a single ethernet packet in the network, On receiving the ethernet packet i see some of the bytes in the frame missing for the reason that the DMA in my MAC faces arbitration issue with the cpu's data and instruction master and hence does not write ceratin packets in SSRAM. In my SOPC builder i had set the arbitration of cpu and data to be 1 and my MAC's DMA with 2.,but inspite of this i still see the frames missing.

So how do i solve this issue? Should i implement a FIFO to store packets and send only when my DMA receives the bus or should i use Nios II/f cpu that has a separate cache for data so that my processor does not interfere much with my MAC?

Should i add a DDR SDRAM in my design connecting it to the MAC's DMA and thereby having the "RESET and EXCEPTION" vector in SOPC to be SSRAM and also having the program,.rodata,.rwdata, stack and heap in NIOS to SSRAM so that my cpu's data and instruction master will acces only the SSRAM and my MAC accesing DDR SDRAM.

I had also downloaded your opencore MAC design and had a look at it. Did you face any of such issues? Can you also tell me what was the memory you had for program,.rodata,.rwdata, stack and heap in NIOS.

Expecting your response to solve my issue.

Regards

Renu.