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New ContributorHello. Running fpga example "MAX 10 User Flash Memory(UFM) Write Operation" on Arrow DECA Development Kit. Problem is the signals from Signal Tap during write operation. Only read operation shows. Is it because of the jtag (built in for deca) ?
11 Replies
ShafiqY_IntelFrequent Contributor
Hi nwee0,
Do you have On-Chip Flash on your design?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_ufm.pdf#page=21
Cheers
nwee0Hello WolfGang. Yes , had use onchip flash in the design. Click on the Data for source[1] to change the value for 0 to 1 to enable write operation.After a while, change back the source[1] value to 0 to disable write operation. But the write signals from signal tap does not shows ? Do that for read , read signals from signal tap shows.
- ShafiqY_Intel
Hi nwee0,
Did you disable the write protection mode? You need to Disable the write protection (write 0 to disable) first before you write into the MAX 10.
cheers
- nwee0
Hello WolfGang. Yes , write '0' to disable write protection. Writing incremental and reading incremental is alright. Just signal tap waveform doesnt shows during write but read shows. Click on the Data for source[1] to change the value for 0 to 1 to enable write operation.After a while, change back the source[1] value to 0 to disable write operation. But the write signals from signal tap does not shows ? Do that for read , read signals from signal tap shows.
- ShafiqY_Intel
Hi nwee0,
I'm apologize for late reply. I didn't realize your reply.
Can you specified what data you want to write? and to which particular address?
(I cannot find the data that you tried to write in top.v)
Cheers
- nwee0
Hello Shafiq . Able to see the write process waveform during incremental write procedure . I basically redo the project and quartus simulation run able to show waveform during incremental write . Thx for the reply. But got question on onchipflash simulation model.
Question : When we create onchipflash memory with simulation model . Can we instantiate the onchipflash and independent simulate it with modelsim (standalone) ? Meaning under modelsim simulation , we write testbench and wrapper for onchipflash ; instantiate the onchipflash model and writing/reading to the memory model ? What are the necessary files for simulation ? Do u have simple example for reading/writing to the onchipflash model (modelsim verilog instatiation) simulation ? I would like to create a memory controller state machine just to access particular address to the onchipfalsh memory.
Thanks .
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