Hello. Running fpga example "MAX 10 User Flash Memory(UFM) Write Operation" on Arrow DECA Development Kit. Problem is the signals from Signal Tap during write operation. Only read operation shows. Is it because of the jtag (built in for deca) ?

Hello Shafiq . Able to see the write process waveform during incremental write procedure . I basically redo the project and quartus simulation run able to show waveform during incremental write . Thx for the reply. But got question on onchipflash simulation model.

Question : When we create onchipflash memory with simulation model . Can we instantiate the onchipflash and independent simulate it with modelsim (standalone) ? Meaning under modelsim simulation , we write testbench and wrapper for onchipflash ; instantiate the onchipflash model and writing/reading to the memory model ? What are the necessary files for simulation ? Do u have simple example for reading/writing to the onchipflash model (modelsim verilog instatiation) simulation ? I would like to create a memory controller state machine just to access particular address to the onchipfalsh memory.

Thanks .

Hi nwee0,

I'm sorry for late reply.

I have not never tried to simulate on chip flash with modelsim(standalone) before.

Based on my experience, simulation model as a whole (I meant is design created with onchipflash IP) is possible. For standalone, I dont think it is possible. You can try it at your own risk.

For example/reference wise, we do not have the similar request for your reference.

Thanks.

Hello tried using altera-modelsim tools but run into instantiation error "# ** Error: (vsim-3033) D:/ProjectUFM/max10_flash/ufm_demo/synthesis/submodules/altera_onchip_flash.v(309): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found." ? Have tried example in forum to resolve it but cant ? Could u have a look why it is not instantiate correctly ?