User1580871742356367
Occasional Contributor
Occasional ContributorForum Discussion
Nathan_R_Intel
Contributor
ContributorHie,
There could be a multiple reasons why this is happening. Basically, if ADC has asserted sync_n and send K28.5 to FPGA, the FPGA will send out dev_sync_n as high.
Hence, please use signal tap to check if sync_n is asserted high correctly when Receiver is receiving K28.5 characters.
Please refer to chapter 6 of the JESD user guide which shows how to debug this issue.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
Do let me know if there is further questions.
Regards,
Nathan
User1580871742356367Occasional Contributor
Occasional ContributorHi Nathen,
#1
1. There will be no SYNC_N asserted by ADC. The SYNC_N is a input at ADC (from FPGA JESD204B Rx to ADC).
2. SYNC_N = dev_sync_n, is generated by FPGA JESD204B Rx link layer.
3. FPGA will dessert dev_sync_n once it received 4+ consecutive K28.5 (x”BC”), which means dev_sync_n will be ‘1’ so as SYNC_N
#2
1. My current issue is that FPGA re-assert dev_sync_n (SYNC_N) after a while(??!)
2. After FPGA re-assert dev_sync_n (SYNC_N), ADC is sending K28.5 again, however,
3. FPGA won’t responding it anymore unless gets reset. Which means,
4. I’ll have to a reset again and then again . . .
#3
Could not find useful debug info from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
So that I’m seeking for the help from the Community! Thank you very much.
Regards,
Ying
