Hello, May I ask was your problem solved? How did you solved it. Thank you very much.

Hie,

There could be a multiple reasons why this is happening. Basically, if ADC has asserted sync_n and send K28.5 to FPGA, the FPGA will send out dev_sync_n as high.

Hence, please use signal tap to check if sync_n is asserted high correctly when Receiver is receiving K28.5 characters.

Please refer to chapter 6 of the JESD user guide which shows how to debug this issue.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf

Do let me know if there is further questions.

Regards,

Nathan