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New ContributorHAN Pilot Terasic Demonstration FPGA socket server ERROR - 2nd GbE unavailable
Hi!
We're having some issues compiling the unmodified demo package delivered with the HAN Pilot board.
In particular SGMII fails compiling, making the secondary GbE port unavailable.
Using Quartus 21.1, below log:
Error (18694): The reference clock on PLL "System:u0|System_altera_eth_tse_211_atpgr2q:tse_mac|System_altera_lvds_211_yghnkdy:i_lvdsio_rx_0|System_altera_lvds_core20_211_rgfbina:core|altera_lvds_core20:arch_inst|altera_lvds_core20_pll:internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.
Is there any specific procedure or setting to have the secondary GbE running?
Thank you for your help!
Sim
2 Replies
AminT_IntelRegular Contributor
Hello,
There is a KDB for this error. Please check on this KDB: https://www.intel.com/content/www/us/en/support/programmable/articles/000080678.html#:~:text=The%20error%20is%20due%20to,below%20in%20the%20reference%20design.
Thank you.
- AminT_Intel
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