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TLu4's avatar
TLu4
Icon for New Contributor rankNew Contributor
6 years ago

Generate DDR2 Controller With UniPHY IP with Quartus 19.1 std edition trouble

I updated Quartus from 18.1 to 19.1 (standard edition). I can't generate DDR2 controller with UniPhy IP from IP Catalog. A MAX 10 is the FPGA in the design. I did following after installing Quarus 1...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Dear @TLu4​ ,

Welcome to Intel Community.

Are you attached some document/picture? I am sorry but I am not able to view any captured window as you mentioned (see below). Can you please help to re-send?

Thanks

Regards,

Aida