Frame reader initialization

Hey Peet,

I was experimenting some more this afternoon and I realized that we will need to take one step back and look again at the hardware setup. I didn't get the STATUS register of the VCO to a "1", this happens when the VCO is outputting correct data. I will check this in detail tonight using signaltap.

So I changed the SOPC settings again, I added a test pattern generator and connected it straight to the VCO (I switched off the control bus again, so also no IRQ problems anymore) and disabled the FR. But still I got no image, normally in this setup we need a nice test pattern as you can see in Experiment3 I added in the attachment. This is the most simple form to use the VCO and TPG, and here it works perfectly. A cause of the problem can be:

-The timing problems we get when the design builds (the current design is more complex then Experiment3, so maybe better constraints needed?). This could be solved by adding the "alt_vip_cvo.sdc" file to the timequest list (when there's a problem with the VCO constraints). This file is included in the IP directory of altera, and sets the timing constraints for the VCO. But when I add this file to the project, timequest ignores all the false path settings because of some error in the sdc (I'm not very good in sdc language so I wasn't able to implement it correctly...). They used this sdc file also in the example for the C3C120 board we shared earlier in this thread.

It's just after some thinking I came to this conclusion, I have no idea if it can help us to solve the problem...

Best and talk soon!

Hans