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Occasional Contributor

3 years ago

Solved

fpga to hps bridge - stratix 10

Hi all, Currently I am working on understanding the HPS-FPGA bridges on the Stratix 10. I have been able to write from the hps to fpga peripherals using the LW bridge. I am now trying to send data f...

tehjingy_Altera
3 years ago
Hi James

Sorry for the late reply, there was a long weekend in my region.

For building the hardware design, you do not need to run the yocto build all the time.
It is meant for building the rootfs for the linux OS.
If there is not changes to the linux portion you could skip the linux building part and only run only the relevant steps.

Regards
Jingyang, Teh

tehjingy_Altera

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Regular Contributor

3 years ago

Hi James

Sorry for the late reply.

Here is what I could gather.

Using the FPGA to HPS bridge you will be accessing the DDR of the HPS.

The addressing will be base on the DDR size :

https://www.intel.com/content/www/us/en/docs/programmable/683222/22-4/example-recommended-system-memory-mapping.html

Unfortunately, there is no design example for the FPGA to HPS bridge for the Stratix10.

However there is an example for the Arria10 board:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html

Regards

Jingyang, Teh

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Occasional Contributor

3 years ago

Hi @JingyangTeh_Altera

Thank you for looking into this for me.

I have a suspicion that the reason my design is not working is because the "Address Map" for my design is not being exported onto the board.

There is a good chance I am programming the board wrong - or incorrectly making the device tree.

What is the proper way to program the Stratix 10 Board with my developed hardware design?

I ask because I am unable to use the Quartus Programmer without losing terminal control of the board.

Thanks,

James