Forum Discussion
Occasional Contributorfpga to hps bridge - stratix 10
Hi James
Sorry for the late reply, there was a long weekend in my region.
For building the hardware design, you do not need to run the yocto build all the time.
It is meant for building the rootfs for the linux OS.
If there is not changes to the linux portion you could skip the linux building part and only run only the relevant steps.
Regards
Jingyang, Teh
Regular ContributorHi James
You could see a list of the address offset under the "Address Map" tab.
Refer to the picture below:
For example the button_pio.s1 via mm_bridge_0.
You will go under the column of the hps.
In the picture you can see it is connected to the hps_h2f_lw bridge. with the offset of 0x600c0.
You would need to go the Address Map of the device and search for the start address for the hps_h2f_lw_bridge.
In this case it is a Cyclone V device the start address of the hps_h2f_lw_bridge is 0xFF200000. (refer to cyclone V Address Map https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html)
From HPS the address of the button_pio.s1 via mm_bridge_0 will be 0xFF2600c0.
For your case you would refer to the Stratix10 Address map :
https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html
Regards
Jingyang, Teh
Occasional ContributorI wrote you a response this morning but it did not seem to get posted.
Thank you for the response. My issue is not with the HPS to FPGA transaction it is with the FPGA to HPS Bridge. I have updated my QSYS design to be the following:
and have added a little verilog function
always @(posedge clk_100_out_clk_clk or posedge rst_controller_reset_out_reset) begin
if (rst_controller_reset_out_reset) begin
internal_reg <= 0;
end else begin
// Perform arithmetic (multiply by 10)
internal_reg <= mm_interconnect_3_qsys_top_fifo_hps_to_fpga_in_writedata * 10;
end
end
assign mm_interconnect_3_qsys_top_fifo_hps_to_fpga_in_writedata = internal_reg;
Simply taking the input multiplying it by ten and sending it to another fifo. My C programs have the following headings...
#define FPGA_BASE_ADDRESS 0xF9000000 // BASE ADDRESS For MASTER
#define FPGA_SPAN 0x00200000 // 2 MB Span
#define INPUT_REG_OFFSET 0x20 // BASE ADDRESS for input reg
#define OUTPUT_REG_OFFSET 0x00 // BASE ADDRESS for output reg
And the outputs show this.
I am getting information across.
I am not sure what is going on. any help with the f2h bridge would be so much help!
Thanks,
James
