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SJeon37's avatar
SJeon37
Icon for New Contributor rankNew Contributor
6 years ago

FPGA logic elements cell delay

Hi, I want to know the minimum delay time between logic elements. With MAX 10 and CYCLONE 10 LP models, about 250 ps came out when one wire was connected from verilog. I would like to know if ther...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Since there is no response from you to the previous question/reply/answer that I have provided. I shall transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Thanks

Best regards,

KhaiY