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SJeon37's avatar
SJeon37
Icon for New Contributor rankNew Contributor
5 years ago

FPGA logic elements cell delay

Hi, I want to know the minimum delay time between logic elements. With MAX 10 and CYCLONE 10 LP models, about 250 ps came out when one wire was connected from verilog. I would like to know if ther...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

The delay depends on the placement and routing of the logic in the design. There is no specific minimum delay value as the value varies for each of the P&R result.

Thanks.

Best regards,

KhaiY