Forum Discussion
New Contributor(FPGA configuration) How much time does Cyclone V GX FPGA take to read data from SPI flash device?
Hi,
table linked in your first post shows 85 ms for C4, ASx4, 100 MHz. This is for uncompressed rbf, compressed rbf is smaller, depending on resource utilization. expect 50 to 90 % in typical applications. I would calculate with uncompressed configuration file size for the time being.
Different clock frequencies (min, typ, max) refer to uncertainty of the internal clock generator. ASx1 has 1/4 throughput of ASx4, if you select fastest internal clock and calculate for worst case (minimal frequency), you end up with 85 *4 *100/42.6 = 798 ms.
Super ContributorHi,
table linked in your first post shows 85 ms for C4, ASx4, 100 MHz. This is for uncompressed rbf, compressed rbf is smaller, depending on resource utilization. expect 50 to 90 % in typical applications. I would calculate with uncompressed configuration file size for the time being.
Different clock frequencies (min, typ, max) refer to uncertainty of the internal clock generator. ASx1 has 1/4 throughput of ASx4, if you select fastest internal clock and calculate for worst case (minimal frequency), you end up with 85 *4 *100/42.6 = 798 ms.
New ContributorHello @FvM,
One last question,
So the required configuration time for the Cyclone V GX FPGA with SPI ASx1 with 42.6 MHz is 798 ms?
In other words, I always use the estimation time from the data sheet to use it as reference and find the configuration time?
However, we have four different DCLK frequency in AS configuration scheme as below:
Why did you use the 42.6 as minimum, why didn't you use 5.3 MHz as minimum as in the figure?
How to know the certainty of the internal clock generator?
Thank you so much for your time @FvM
