Forum Discussion
New Contributor(FPGA configuration) How much time does Cyclone V GX FPGA take to read data from SPI flash device?
Hi,
table linked in your first post shows 85 ms for C4, ASx4, 100 MHz. This is for uncompressed rbf, compressed rbf is smaller, depending on resource utilization. expect 50 to 90 % in typical applications. I would calculate with uncompressed configuration file size for the time being.
Different clock frequencies (min, typ, max) refer to uncertainty of the internal clock generator. ASx1 has 1/4 throughput of ASx4, if you select fastest internal clock and calculate for worst case (minimal frequency), you end up with 85 *4 *100/42.6 = 798 ms.
Super Contributorquite simple, you need to know which configuration scheme is actually used in your board. SPI means AS, but do you have AS×1 or AS×4 hardware, are you providing user clock 100 MHz or less, or relying on internal configuration clock?
New ContributorHello @FvM ,
The answers to your questions as below:
1. Which configuration scheme is actually used in your board. SPI means AS, but do you have AS×1 or AS×4 hardware
Ans/ We use ASx1 of SPI.
2. are you providing user clock 100 MHz or less, or relying on internal configuration clock?
Ans/ we are relying on the internal clock However, in the datasheet it shows the following
Are we able to configure the DCLK? And what is the difference between them, I mean why we have many minimums, typicals and maximums?! Now I am more confused, how we choose between them, and how can I learn the configuration time? Or it depends on the FPGA module?
FYI, We are using 5CGXFC4C6U19I7N with Member code C4, with 50K of logic elements
The final question, Now, how to calculate the configuration time and what it is for example?
Much appreciate your support @FvM
