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Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

FPGA can work at >500Mhz?

Hi everyone, If my design which use less resource of FPGA, it can run more than 500Mhz? For example, my fpga is Arria V, my design use resource less than 15%, and I only need few resource to r...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
6 years ago

Yes, the 625/525MHz global clock max will give you an upper limit of how fast your logic can run.

Running at 80% to 90% of those limits will require careful thought on how you architect your device.

You will need (probably) lots of pipelining, and need to partition logical functions in the pipeline carefully.

Getting above 100MHz is not hard these days with a high end FPGA like the ArriaV; 200-300MHz should be achievable with some thought.

So you might think about a 2X wider pipeline running at 250MHz instead of a 1X pipeline at 500MHz. The former should be a lot easier.

  • Lambert's avatar
    Lambert
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi ak6dn,

    Thanks, now I ensure something and I will try to do something to make my design can run correctly above 500Mhz, and verify mu design function.

    ​

    Best regards,

    lambert