FPGA- SDC creation for 0.00039MHz clk

Instead of using a slow clock for your sensor detection module, you update it only when clk_en is high:

always @(posedge clk or negedge reset_n) begin

if (!reset_n) begin

sensor_state <= 0;

end else if (clk_en) begin

sensor_state <= sensor_input; // Sample the sensor input at 390 Hz

end

end

If you need to detect a rising edge of the sensor input, you can do:

reg sensor_prev; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin sensor_prev <= 0; end else if (clk_en) begin sensor_prev <= sensor_input; end end wire sensor_rising_edge = clk_en & sensor_input & ~sensor_prev;

This will trigger a pulse only when the sensor input rises at 390 Hz.