Forum Discussion
New ContributorFPGA- SDC creation for 0.00039MHz clk
Instead of using a slow clock for your sensor detection module, you update it only when clk_en is high:
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sensor_state <= 0;
end else if (clk_en) begin
sensor_state <= sensor_input; // Sample the sensor input at 390 Hz
end
end
If you need to detect a rising edge of the sensor input, you can do:
reg sensor_prev; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin sensor_prev <= 0; end else if (clk_en) begin sensor_prev <= sensor_input; end end wire sensor_rising_edge = clk_en & sensor_input & ~sensor_prev;
This will trigger a pulse only when the sensor input rises at 390 Hz.
Super ContributorI believe that it is because you are constraining the clock to be too slow that is causing this problem. My suggestion is for you to use clock enable instead:
Example 1:
- reg [16:0] counter; reg clk_en; always @(posedge clk or negedge reset_n) begin if (!reset_n) begin counter <= 0; clk_en <= 0; end else if (counter == 127999) begin // Divide 50 MHz to 390 Hz counter <= 0; clk_en <= 1; end else begin counter <= counter + 1; clk_en <= 0; end end. Adjust 127999 if using a different base clock frequency.
Example 2:
Use the generated clk_en to enable the logic that would typically run on the 390 Hz clock:
verilog
always @(posedge clk or negedge reset_n) begin if (!reset_n) begin slow_logic_state <= 0; end else if (clk_en) begin slow_logic_state <= next_slow_logic_state; end end
Thanks
abinaya_PIn my design, the slower clock is used as clock for one module, in this rising edge we are detecting the sensor input.
if we use the clk_en method how do we use this signal as clock?
Regards,
Abinaya
