finding difficulty in porting dsign from ArriaII dev board to Cylone IV dev board

hey guys,

I am trying to port a design consisting a TSE core from arria 2 dev board to cyclone 4 dev board. The design is just a loopback from a system to board and back to the system. In promiscuous mode. the design works fine in arria 2 board but not responding on cyclone 4 board.

In arria 2 the design is working but signal tap is not showing the action on the IP core signals (like ff_tx_data or ff_rx_data etc).

any suggestions ...

thanks...