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MCoen
New Contributor
New ContributorFifo interface DE1-SoC
Hi, I'm currently designing a fifo interface between the HPS and the FPGA of the DE1-SoC. All the programming is done but I'm constantly getting the value 2097152 back in my HPS with the status o...
MuhammadAr_U_Intel
Contributor
ContributorHi @MCoen
I am looking at this case, may I know if the FIFO is reset the beginning ?
Did you monitor the FIFO signal and your FSM signals in signltap ?
Here is another forum thread on rocket board discussing about read/ wrtie to on chip fifo from HPS, see if this help to answer your question.
https://forum.rocketboards.org/t/how-to-read-and-write-an-on-chip-fifo-from-hps-arm/849
Thanks,
Arslan
