FIFO based module implementation Error. Results not as expected, using Quartus Prime Software and vJTAG implementation method.

To pause for 10 clock cycles you need to implement a counter to count them. This will need at least 4 flip-flops. You can then continue to do whatever next.

$display is only used for simulation. It has no effect or use in synthesisable code.

Blocking vs non-blocking is a very common issue, frequently misunderstood. You always need to consider what the gates are going to look like when writing your code. This will help you understand what values each storage element - flip-flop - will hold after each clock cycle.

Have a look at:

http://www.asic-world.com/tidbits/blocking.html

Cheers,

Alex