FIFO based module implementation Error. Results not as expected, using Quartus Prime Software and vJTAG implementation method.

Are you simply simulating this code? Or are you trying to synthesise this code and put it into a device? Does your simulation work?

The code, as is, is not going to do some of the things your comments indicate you want it to do - not in a device anyway. You cannot us #10 to delay by 10 'timesteps' (clock cycles?). These delays are for simulation only.

I recommend you code everything with nonblocking statements. I can see you've suggested you need to keep the order of statements. However, they're doing as you want. Change them all to nonblocking and make sure the simulation works. Remember to only update each register once per conditional branch (if / else). Coded cleanly you can do everything with the nonblocking operator - certainly everything you're trying to do here.

I see a number of other bits of the code that suggest to me that you've not simulated this - I could be wrong. Make sure the simulation behaves before proceeding to a device.

Cheers,

Alex