Honored Contributor
Honored ContributorYes I used synchronous FIFO mode in the FT223H for the data channel. A tricky data sheet to read, so much in it, so many modes :
3.4.2 FT2232H pins used in an FT245 Style Synchronous FIFO Interface : ADBUS[7:0] I/O D7 to D0 bidirectional FIFO data. I attach a cropped SignalTapII recording, being clocked at 120MHz. clk_ftdi is a 60 MHz Clock driven from the FTDI chip. The data being sent is counting up, the remaining byte-count counting down with each byte. https://www.alteraforum.com/forum/attachment.php?attachmentid=5807 For short bursts SignalTapII shows the data being clocked in or out at every clock, then there is a variable gap between the bursts. How much of this is USB related and how much PC being other-wise occupied, I do not know. https://www.alteraforum.com/forum/attachment.php?attachmentid=5808 With up-transfers of 1k word x 16 bit data (being scaled and then converted from 64bit floating-point data in an Apl interpreter), followed by a command to read the same block back, convert it to 64-bit floating point, error checked, and displayed on a graph, a 1.6GHz Windows 7 64bit lap-top (running a 32bit Apl interpreter) can do this continually every 50ms, with transfer delay jitter just starting to go up. Down at 20 ms the system is just not keeping up. The YouTube video was captured at 10 Hz frame rate, so I used 100ms repeat time for this.
