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Altera_Forum
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8 years ago

Failed programming at 85%

Hello All, I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Yes, the report I showed was from the Compilation Report -> Timing Analyzer -> Clocks section.

I added a .sdc file as follows:set_time_format -unit ns -decimal_places 3

create_clock -name {board_clock} -period 20.000 -waveform { 0.000 10.000 } [get_ports { board_clock }]

derive_pll_clocks -create_base_clocks

derive_clock_uncertainty

And I did a compilation again. Got the same report as before and the following warnings:Critical Warning(18655): There are 48 unused TX channels in the design.

Critical Warning(17951): There are 48 unused RX channels in the design.

Critical Warning(332148): Timing requirements not met

I still have the same programming error at 85%. And the Message Window does not show anything about the programming error.