Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFailed programming at 85%
Hello All, I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP...
Altera_ForumHonored Contributor
Honored ContributorEven with the PLL settings, you still have to have a .sdc for timing closure. The report you show may be showing the clock settings from the PLL settings (it's not clear which part of the Compilation Report you're showing; is it from the timing analyzer folder?), but as the messages you posted say, timing analysis is using a 1 GHz base clock, not these clocks.
But as you say, it still doesn't explain why programming is failing. As I asked, did you check the Messages window to see if there was an error reported during programming?
