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Altera_Forum
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8 years ago

Failed programming at 85%

Hello All, I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks.

However, I'm still not clear. Even though I don't have a .sdc file, the clocks are still correct as they were specified when I generated the IOPLL core. Please see the attached screen shot.

https://alteraforum.com/forum/attachment.php?attachmentid=15721&stc=1

And if the lack of a clock constraint is the issue, why didn't I have an error when I commented out the red line? And the LED was still blinking as expected.

Thanks,

Binh