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Altera_Forum
Honored Contributor
Honored ContributorFailed programming at 85%
Hello All, I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP...
Altera_ForumHonored Contributor
Honored ContributorYou have not included a .sdc file in your design, so it has set the base clock constraint for the incoming clock to be 1 GHz with all other clocks in the design based off of that. So your design is most likely failing timing.
Check the messages window in Quartus to get an idea of why programming might be failing.
