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Contributor

1 year ago

F2SDRAM : mSGDMA endian issue and SDRAM reading/writing issue

Hi I'm working on CycloneVsoc Dev Kit baremetal system Now I want to use F2H sdram to transmit my data. The draft system Interconnection: HPS host master | | host order | SelfIP...

Board Debug

Fpga Devkit

aikeu

Regular Contributor

1 year ago

Hi CAlex,

Maybe can check out this example link which is similar to the previous link showcasing msgdma using Nios as reference.

https://www.macnica.co.jp/en/business/semiconductor/articles/intel/129345/

Thanks.

Regards,

Aik Eu

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F2SDRAM : mSGDMA endian issue and SDRAM reading/writing issue

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