F2SDRAM : mSGDMA endian issue and SDRAM reading/writing issue

Hi CAlex,

I think you can use the same software code from this design example as reference to perform the transfer for your baremetal application:

https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335

The sdram is refering to the external sdram which is the DDR for your case.

If checking that specific start address for your baremetal application which loaded to the DDR, you can see the same application content which you have built.

Thanks.

Regards,

Aik Eu