Forum Discussion

CAlex's avatar
CAlex
Icon for Contributor rankContributor
1 year ago

F2SDRAM : mSGDMA endian issue and SDRAM reading/writing issue

Hi I'm working on CycloneVsoc Dev Kit baremetal system Now I want to use F2H sdram to transmit my data. The draft system Interconnection: HPS host master | | host order | SelfIP...
Board Debug
Fpga Devkit
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi CAlex,


I think you can use the same software code from this design example as reference to perform the transfer for your baremetal application:

https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335


The sdram is refering to the external sdram which is the DDR for your case.

If checking that specific start address for your baremetal application which loaded to the DDR, you can see the same application content which you have built.


Thanks.

Regards,

Aik Eu


CAlex's avatar
CAlex
Icon for Contributor rankContributor
1 year ago

Hi

I cant use this example for I only get lite edition.