Forum Discussion
New ContributorExample Design Fails Compilation Due To "Timing Requirements NOT MET"
Hi guys,
I have recently bought Intel Stratix 10 MX FPGA Development Kit.
The official link is included here:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-mx.html
I want to learn about DDR[4] DIMM design and testing.
I can see that there is a package for an example design, from the link above.
May I ask if anybody can update the example design to the newer version of "Quartus (Quartus Prime Pro 22.1)" please ??
Because I think the provided example design is old/outdated and failed the timing analysis during compilation (i.e. IP upgrade ??).
I mean I could have spent a lot of time trying to see where the timing fails, BUT I think that would defeat my purpose of buying this kit and learn the example design.
Any help would be appreciated,
Thanks,
Have a nice day,
TH
3 Replies
AdzimZM_AlteraRegular Contributor
Hi TH,
The example design from the package cannot be updated and the design can usually run on a same version as it's been generated.
The errors are expected if you're using later version of Quartus.
I think you're submitting similar case in this link right:
I will continue to assist you on that case and let this case to be on community support.
Regards,
Adzim
th_fpga_2022Hi AdzimZM_Intel,
Thank you,
Have a nice day,
Tung Ho
- AdzimZM_Altera
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
