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th_fpga_2022's avatar
th_fpga_2022
Icon for New Contributor rankNew Contributor
3 years ago

Example Design Fails Compilation Due To "Timing Requirements NOT MET"

Hi guys, I have recently bought Intel Stratix 10 MX FPGA Development Kit. The official link is included here: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi TH,


The example design from the package cannot be updated and the design can usually run on a same version as it's been generated.

The errors are expected if you're using later version of Quartus.


I think you're submitting similar case in this link right:

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-To-Simulate-Example-Designs/m-p/1391535#M22565

I will continue to assist you on that case and let this case to be on community support.


Regards,

Adzim


  • th_fpga_2022's avatar
    th_fpga_2022
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi AdzimZM_Intel,

    Thank you,

    Have a nice day,

    Tung Ho