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AATLI3's avatar
AATLI3
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7 years ago

Ethernet Communication Interface for Cyclone IV GX FPGA on DE2i-150 board

I would like to implement an Ethernet core on DE2i-150 which provides Ethernet support via a Marvell 88E1111 Ethernet PHY chip. In order to start practicing, I just want to print the source and desti...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Volkan, Take your time. You can refer to AN647 link that I shared. It does explain on the Ethernet packet on the MAC All the reference design that I shared typically performing a TX to RX loopback test. So, the first data packet that you read back will be the destination address and source address. So, reference design is still a good start for you. Thanks. Regards, dlim