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AATLI3's avatar
AATLI3
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6 years ago

Ethernet Communication Interface for Cyclone IV GX FPGA on DE2i-150 board

I would like to implement an Ethernet core on DE2i-150 which provides Ethernet support via a Marvell 88E1111 Ethernet PHY chip. In order to start practicing, I just want to print the source and desti...
Deshi_Intel's avatar
Deshi_Intel
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6 years ago
Hi Ali, I think the best way to help you is to learn Ethernet via reference design but unlikely you will find the exact reference design that match with DE2i-150 board directly. However, you should be able to find something close. I am not sure which Ethernet protocol or mode that you are testing but I would recommend to start with Intel triple speed Ethernet (TSE) IP reference design that interact with Marvell 88E1111 PHY chip. Some of the useful reference design link are as below. https://fpgawiki.intel.com/wiki/Scalable_TSE_without_1588_Design_Example https://fpgawiki.intel.com/wiki/Category:Interfaces https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an647.pdf Happy learning ! Thanks. Regards, dlim
AATLI3's avatar
AATLI3
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6 years ago

Hi dlim

In fact, I am not fully mastering the FPGA jargon, but I think I want to write TSE MAC itself, the Finite State Machine, (Preamble, Start Frame Delimiter, Destination Address, Source Address, etc ...). The TSE MAC seems to abstract all details, please correct me if i miss anything.

In the first stage, the only thing I want to do is to print the source and destination addresses through JTAG. But I want to do this as soon as the destination address comes from FSM.

- Volkan