Forum Discussion
A_MISHRA
New Contributor
New ContributorError(175019): Illegal constraint of I/O pad to the location PIN_K12
Custom design using Arria 10 SOC, 10AS066KF40- The clkout pin (PLL_3H_CLKOUT0P,PLL_3H_CLKOUT0,PLL_3H_FB0/LVDS3H_15P/DQ68 ) which is also defined as LVDS in pin description, when used as LVDS differ...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
Kindly check PIN _K12 is in 3V IO bank. If it is in 3VIO bank there is no LVDS IO support for Arria 10 .
A_MISHRANew Contributor
New ContributorThank you for your kind reply. Actually issue was with pin mapping. We have used ADS42LB69, its having LVDS clocks and data. By mistake we have mapped P(positive) pin of ADC data line to LVDS3H_15N means Positive pin was mapped to Negative pin of LVDS Bank 3H and vice versa. After swapping these pins in pin planner issue was resolved.
