Forum Discussion
Niko3
Occasional Contributor
1 year agoerror in ModelSim?
I am using Quartus II 64-Bit Version 13.0.1 to change a design for a MAX3000a series chip and I want to simulate it with ModelSim-Altera which is contained in the Quartus II software. Simulation fo...
- 1 year ago
Hi,
Inside the testbench myProject_tb_1.v, make sure the module name also myProject_tb_1.
Thanks,
Regards,
Sheng
ShengN_altera
Super Contributor
1 year agoHi,
You can include .vo file in Project Navigator -> Files.
Go to Assignments -> Settings -> EDA Tool Settings -> Simulation and make sure the the testbench name correct which is myProject_tb instead of myProjekt_tb.
Then run compilation and go to Tool -> Run Simulation Tool -> Gate Level Simulation
Attached the design and result i got below.
Thanks,
Regards,
Sheng
Niko3
Occasional Contributor
1 year agoHi,
thank you very much. What a stupid error!
A final question: modelsim displays the signals in a fuzzy sequence. Where is the best location to reorder the sequence of signals in a functionally reasonable sequence?