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Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

error in ModelSim?

I am using Quartus II 64-Bit Version 13.0.1 to change a design for a MAX3000a series chip and I want to simulate it with ModelSim-Altera which is contained in the Quartus II software. Simulation fo...
Fpga Devkit
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    Inside the testbench myProject_tb_1.v, make sure the module name also myProject_tb_1.


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


University Program VWF Simulations is legacy simulator. Probably some of the IP upgradation is not included in this legacy simulator. I would suggest to use the modelsim or questasim simulator.


Thanks,

Regards,

Sheng


  • Niko3's avatar
    Niko3
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,

    I chose University Program VWF because I'm not familiar with VHDL to write a testbench and because VWF provides a simple interactive method to generate waveforms. The single bits of a bus can be grouped and then a value can be defined for the group.

    I had a look at modelsim and are missing a simple method to generate waveforms for buses. The design contains some 4bit buses as input which have to be defined for a testbench. The only graphical way (edit -> create/modify waveform -> ...) to generate waveforms I found is to define every single bit of the buses which is very tedious.

    Do you know a better method?