Error: Conflict PLL, Custom PHY IP 4 Lane GE with Quartus Prime Standard 30-Day Free Trial

Hello Xiaoyan,

I am working with the Cyclone V (5CGXFC5C6F23I7) and have updated the IO Assignment, as shown in the attached file.

I am using Custom PHY IP to generate Gigabit Ethernet Mode (GIGE) with both 4-lane and 5-lane SGMII configurations.

For 4-lane SGMII, I assigned the pins to GXB 1, 2, 3, 4.
For 5-lane SGMII, I assigned the pins to GXB 0, 1, 2, 3, 4.
However, I encountered errors during Place and Route (PnR):

With 4-lane SGMII (GXB 1, 2, 3, 4):

PnR fails with the following error (details in the attached file):
Error (14566): The Fitter cannot place 4 periphery components due to conflicts with existing constraints (4 Clock Divider(s)).
With 5-lane SGMII (GXB 0, 1, 2, 3, 4):

PnR also fails.
Please help me resolve these issues.

Best regards,
Le